Boolean gates, which may be implemented using transistors, form a basic element of many integrated circuits. For example, when the gates are properly implemented, they will retain an input value, and therefore enable the storage of data. This simple concept is the basis of a random access memory (RAM), and also makes it possible to create a wide variety of other useful circuits. For example, flip-flops, which are well known in the art, are also created from predetermined arrangements of gates and enable a variety of functions to be implemented in an integrated circuit. For example, flip-flops may be used in shift registers, counters, frequency dividers and sequence detectors, among a number of other applications.
However, certain flip-flops may encounter a problem with unintended oscillation. One way of overcoming the problem of oscillation is to use two back-to-back flip-flops, commonly called a master-slave flip-flop. An example of a conventional master-slave flip-flop is shown in FIG. 1. In particular, a master flip-flop 102 and a slave flip-flop 104 receive clock signals generated by a pair of inverters 106 and 108. The master flip-flop 102 comprises a first tri-state buffer 110, which receives an input data signal D, and an inverter 112. The output of the inverter is coupled to a second tri-state buffer 114 to create a latch. The output of the inverter 112 is also coupled to a first tri-state buffer 116 of the slave flip-flop 104. The first tri-state buffer 116 of the slave flip-flop 104 is coupled to an inverter 118, the output of which is coupled to a second tri-state buffer 120 of the slave flip-flop 104 to create a latch for the slave flip-flop. The output of the tri-state buffer 120 is coupled to an inverter 122, which generates an output signal Q.
In a master-slave flip-flop, the master flip-flop operates as an input latch, while the output is slaved to the master during a half of each clock cycle. An important feature of a master-slave-flip-flop is that the complement of the clock pulse is fed to the slave flip-flop. Therefore, the outputs from the master flip-flop are only “seen” by the slave flip-flop when the clock signal is high. That is, on the low-to-high transition of the clock, the outputs of the master are fed through the slave flip-flop. By employing an edge-triggered master-slave flip-flop, the moment when all flip-flops change state may be controlled.
One commonly used flip-flop is the J-K flip-flop. A J-K flip-flop may perform the function of other conventional flip-flops, such as D, R-S or T type flip-flops. It has the input-following characteristics of a clocked D flip-flop, but has two inputs, traditionally labeled J and K. If J and K are different, then the output Q takes the value of J at the next clock edge. If J and K are both low, then no change occurs. If J and K inputs are both high at the clock edge, then the output will toggle from one state to the other. A J-K flip-flop may perform the functions of the set/reset flip-flop and has the advantage that there are no ambiguous states. Finally, a J-K flip-flop may also act as a T flip-flop to accomplish toggling action if the J and K inputs are tied together. J-K flip-flops are also often configured as master-slave flip-flops in order to overcome the problem with oscillation. Accordingly, the single change of state may occur when J=K=1, preventing oscillation between states Q=0 and Q=1 at successive clock pulses.
One category of integrated circuits which often employs flip-flops is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. Programmable logic circuits of a PLD comprise gates which are configurable by a user of the circuit to implement a desired circuit design. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. However, an error in the configuration memory cells may cause the PLD to function improperly. When a circuit enabling error correction is implemented in a programmable logic device, the programmable logic device does not have to be completely reconfigured, possibly causing many seconds of system downtime.
Certain applications of programmable logic devices, such as military, aerospace, and high-reliability communications, require detection of errors even when the likelihood of such an occurrence is extremely low. Furthermore, applications running in redundant systems require fast indication of a single event upset (SEU) in order to minimize the impact upon operation. In many cases, fast correction with minimal impact upon operation is also required. Even the rare SEU must be detected for some high-reliability systems so that appropriate system measures may be taken to ensure very high uptime. In certain applications, automatic correction of errors may also be a significant advantage. When processing real-time streaming data such as a video signal, for example, automatic correction of errors allows operation to continue without the need for a system reset. Among other benefits, the correction of errors in circuits allows much faster system recovery time of a programmable logic device.
Accordingly, there is a need for an improved circuit for and method of preventing an error in a flip-flop.